Hardware Power ON
3,0>
3,0>@(#) POST 3.9.30 2002/10/25 14:04
3,1>
3,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
3,1>@(#) POST 3.9.30 2002/10/25 14:04
3,0>
    SelfTest Initializing (Diag Level 10, ENV 0000ff00) IMPL 0011 MASK a0
3,1>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
3,0>Board 3 CPU FPROM Test
3,1>
    SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK a0
3,0>Board 3 Basic CPU Test
3,0>    Set CPU UPA Config and Init SDB Data
3,0>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,0>Board 3 MMU Enable Test
3,0>    DMMU Init
3,0>    IMMU Init
3,0>    Mapping Selftest Enabling MMUs
3,0>Board 3 Ecache Test
3,0>    Ecache Probe
3,0>    Ecache Tags
3,1>Board 3 CPU FPROM Test
3,1>Board 3 Basic CPU Test
3,1>    Set CPU UPA Config and Init SDB Data
3,1>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,1>Board 3 MMU Enable Test
3,1>    DMMU Init
3,1>    IMMU Init
3,1>    Mapping Selftest Enabling MMUs
3,1>Board 3 Ecache Test
3,1>    Ecache Probe
3,1>    Ecache Tags
3,0>    Ecache Quick Verify
3,1>    Ecache Quick Verify
3,0>    Ecache Init
3,1>    Ecache Init
3,0>    Ecache RAM
3,1>    Ecache RAM
3,0>    Ecache Address Line
3,0>    Configure Ecache Limit
3,0>Ecache Size = 00800000,  Limited to 00800000 
3,0>Board 3 FPU Functional Test
3,0>    FPU Enable
3,0>Board 3 Board Master Select Test
3,0>    Selecting a Board Master
3,0>Board 3 FireHose Devices Test
3,1>    Ecache Address Line
3,1>    Configure Ecache Limit
3,1>Ecache Size = 00800000,  Limited to 00800000 
3,1>Board 3 FPU Functional Test
3,1>    FPU Enable
3,1>Board 3 Board Master Select Test
3,1>    Selecting a Board Master
3,0>Board 3 Address Controller Test
3,0>    AC Initialization
3,0>    AC DTAG Init
3,0>Board 3 Dual Tags Test
3,0>    AC DTAG Init
3,0>Board 3 FireHose Controller Test
3,0>    FHC Initialization
3,0>Board 3 JTAG Test
3,0>    Verify System Board Scan Ring
3,0>Board 3 Centerplane Test
3,0>    Centerplane Join
3,0>Setting JTAG Master
3,0>Clear JTAG Master
3,0>Board 3 Setup Cache Size Test
3,0>    Setting Up Cache Size
3,0>Board 3 System Master Select Test
3,0>    Setting System Master
3,0>POST Master Selected (JTAG,CENTRAL)
3,0>Board 16 Clock Board Test
3,0>    Clock Board Initialization
3,0>    Clock Board Temperature Check
3,0>Board 16 NVRAM Devices Test
3,0>    M48T59 (TOD) Init
3,0>Board 3 System Board Probe  Test
3,0>    Probing all CPU/Memory BDA
3,0>    Probing System Boards
3,0>    Probing CPU Module JTAG Rings
3,0>Setting System Clock Frequency
3,0>	CPU Module mid 6 Checked in OK (speed code = 3)
3,0>	CPU mid 7 Version=00170011.a0000507
3,0>	CPU Module mid 7 Checked in OK (speed code = 3)
3,0> ******** Clock Reset - retesting 
3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400
3,0>
3,0>@(#) POST 3.9.30 2002/10/25 14:04
3,1>
3,0>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
3,1>@(#) POST 3.9.30 2002/10/25 14:04
3,0>
    SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK a0
3,1>Copyright 2002 Sun Microsystems, Inc. All rights reserved.
3,0>Board 3 CPU FPROM Test
3,1>
    SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK a0
3,0>    CPU/Memory Board FPROM Checksum Test
3,1>Board 3 CPU FPROM Test
3,1>    CPU/Memory Board FPROM Checksum Test
3,0>Board 3 Basic CPU Test
3,0>    FPU Registers and Data Path Test
3,0>    Instruction Cache Tag RAM Test
3,1>Board 3 Basic CPU Test
3,1>    FPU Registers and Data Path Test
3,1>    Instruction Cache Tag RAM Test
3,0>    Instruction Cache Instruction RAM Test
3,1>    Instruction Cache Instruction RAM Test
3,1>    Instruction Cache Next Field RAM Test
3,0>    Instruction Cache Next Field RAM Test
3,1>    Instruction Cache Pre-decode RAM Test
3,0>    Instruction Cache Pre-decode RAM Test
3,1>    Data Cache RAM Test
3,0>    Data Cache RAM Test
3,1>    Data Cache Tags Test
3,1>    DMMU Registers Access Test
3,1>    DMMU TLB DATA RAM Access Test
3,1>    DMMU TLB TAGS Access Test
3,1>    IMMU Registers Access Test
3,1>    IMMU TLB DATA RAM Access Test
3,1>    IMMU TLB TAGS Access Test
3,1>    Set CPU UPA Config and Init SDB Data
3,1>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,1>Board 3 MMU Enable Test
3,1>    DMMU Init
3,1>    IMMU Init
3,1>    Mapping Selftest Enabling MMUs
3,1>Board 3 Ecache Test
3,1>    Ecache Probe
3,1>    Ecache Tags
3,0>    Data Cache Tags Test
3,0>    DMMU Registers Access Test
3,1>    Ecache Quick Verify
3,0>    DMMU TLB DATA RAM Access Test
3,0>    DMMU TLB TAGS Access Test
3,0>    IMMU Registers Access Test
3,0>    IMMU TLB DATA RAM Access Test
3,0>    IMMU TLB TAGS Access Test
3,0>    Set CPU UPA Config and Init SDB Data
3,0>	SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0
3,0>Board 3 MMU Enable Test
3,0>    DMMU Init
3,0>    IMMU Init
3,0>    Mapping Selftest Enabling MMUs
3,0>Board 3 Ecache Test
3,0>    Ecache Probe
3,0>    Ecache Tags
3,0>    Ecache Quick Verify
3,1>    Ecache Init
3,0>    Ecache Init
3,1>    Ecache RAM
3,0>    Ecache RAM
3,1>    Ecache 6N RAM Pattern Test
3,0>    Ecache 6N RAM Pattern Test
3,1>    Ecache Address Line
3,1>    Configure Ecache Limit
3,1>Ecache Size = 00800000,  Limited to 00800000 
3,1>Board 3 FPU Functional Test
3,1>    FPU Enable
3,1>Board 3 Board Master Select Test
3,1>    Selecting a Board Master
3,0>    Ecache Address Line
3,0>    Configure Ecache Limit
3,0>Ecache Size = 00800000,  Limited to 00800000 
3,0>Board 3 FPU Functional Test
3,0>    FPU Enable
3,0>Board 3 Board Master Select Test
3,0>    Selecting a Board Master
3,0>Board 3 FireHose Devices Test
3,0>    PROM Datapath Test
3,0>    FHC CPU SRAM Test
3,0>Board 3 Address Controller Test
3,0>    AC Registers Test
3,0>    AC Initialization
3,0>    Memory Registers  Test
3,0>    Memory Registers Initialization Test
3,0>    AC DTAG Init
3,0>Board 3 Dual Tags Test
3,0>    AC DTAG Test
3,0>    AC DTAG Init
3,0>Board 3 FireHose Controller Test
3,0>    FHC Initialization
3,0>Board 3 JTAG Test
3,0>    Verify System Board Scan Ring
3,0>Board 3 Centerplane Test
3,0>    Centerplane and Arbiter Check Test
3,0>Setting JTAG Master
3,0>Clear JTAG Master
3,0>    Centerplane Join
3,0>Setting JTAG Master
3,0>Clear JTAG Master
3,0>Board 3 Setup Cache Size Test
3,0>    Setting Up Cache Size
3,0>Board 3 System Master Select Test
3,0>    Setting System Master
3,0>POST Master Selected (JTAG,CENTRAL)
3,0>Board 16 Clock Board Test
3,0>    Clock Board Registers Test
3,0>    Clock Board Initialization
3,0>    Clock Board Temperature Check
3,0>Board 16 NVRAM Devices Test
3,0>    M48T59 (TOD) Init
3,0>    M48T59 (TOD) Functional Part 1 Test
3,0>    NVRAM(Non-Destructive) Test
3,0>Board 3 System Board Probe  Test
3,0>    Probing all CPU/Memory BDA
3,0>    Probing System Boards
3,0>    Probing CPU Module JTAG Rings
3,0>Setting System Clock Frequency
3,0>	CPU Module mid 6 Checked in OK (speed code = 3)
3,0>	CPU mid 7 Version=00170011.a0000507
3,0>	CPU Module mid 7 Checked in OK (speed code = 3)
3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400
3,0>TESTING BOARD 1
3,0>Board 1 JTAG Test
3,0>    Verify System Board Scan Ring
3,0>Board 1 Centerplane Test
3,0>    Centerplane Check
3,0>Board 1 Address Controller Test
3,0>    AC Registers Test
3,0>    AC Initialization
3,0>Setting Freq to 25MHZ
3,0>    Memory Registers  Test
3,0>    Memory Registers Initialization Test
3,0>    AC DTAG Init
3,0>Board 1 FireHose Controller Test
3,0>    FHC Initialization
3,0>Board 1 NVRAM Devices Test
3,0>    M48T59 (TOD) Init
3,0>    M48T59 (TOD) Functional Part 1 Test
3,0>    NVRAM(Non-Destructive) Test
3,0>Re-mapping to Local Device Space
3,0>Begin Central Space Serial Port access
3,0>Enable AC Control Parity
3,0>Hotplug Trigger Test
3,0>Init Counters for Hotplug
3,0>Board 3 Cross Calls Test
3,0>    Cross Calls Test
3,0>Displaying PROM Versions
3,0>Slot 1 IO Type 4    FCODE 1.8.29 2001/6/18 17:26  iPOST 3.4.29 2001/6/18 17:
49
3,0>Slot 3 CPU/Memory   OBP   3.2.30 2002/10/25 14:03  POST  3.9.30 2002/10/25 1
4:04
3,0>Board 3 Environmental Probe Test
3,0>    Environmental Probe
3,0>ERROR: TEST=Environmental Probe,SUBTEST=Environmental Probe ID=1f.1
3,0>Component under test: Board 3 System Interrupt
3,0>Peripherial Power Supply PPSS_0 Failed
3,0>ERROR: TEST=Environmental Probe,SUBTEST=Environmental Probe ID=1f.1
3,0>Component under test: Board 3 System Interrupt
3,0>Peripherial Power Supply PPSS_0 Failed
3,0>Checking Power Supply Configuration
3,0>Power is more than adequate, load 2 ps 3
3,0>
3,0>	System Environmental Status
3,0>-----------------------------------------------------------------
3,0> Slot  Board Type    Temp   PS Stat      Perph PS
3,0>-----------------------------------------------------------------
3,0>  0  | Empty       |      |            | PP0 FAIL   |
3,0>  1  |+IO Type 4   | <32  | PS1 OK     | PP1 N_PRES |
3,0>  2  | Empty       |      |            |            |
3,0>  3  |+CPU/Memory  | <33  | PS3 OK     |            |
3,0>  4  | Empty       |      |            |            |
3,0>  5  | Empty       |      | PS5 OK     |            |
3,0>  6  | Empty       |      |            |            |
3,0>  7  | Empty       |      |            |            |
3,0> 16  | Clock Board | <30  |            |            |
3,0>-----------------------------------------------------------------
3,0>
3,0>	Precharge and Peripheral Power Supply Status
3,0>-----------------------------------------------------------------
3,0> V5_PCH   V3_PCH   V12_PCH  V5_PPCH  V5_AUX   V12_P    V5_P
3,0>-----------------------------------------------------------------
3,0> FAIL   | FAIL   | FAIL   | FAIL   | FAIL   | FAIL   | FAIL   |
3,0>-----------------------------------------------------------------
3,0>
3,0>	Miscellaneous Sensor Status
3,0>-----------------------------------------------------------------
3,0> RK_FAN   AC_FAN   KEY_FAN  CLK_33   CLK_50   NOT_BD_PRES
3,0>-----------------------------------------------------------------
3,0> FAIL   | OK     | OK     | OK     | OK     | ONE    |
3,0>-----------------------------------------------------------------
3,0>Reconfig memory due to POR or CLOCK RESET
3,0>Reconfig memory due to DIAG_LEVEL
3,0>Board 3 Probing Memory SIMMS Test
3,0>    Probe SIMMID
3,0>	Populated Memory Bank Status
3,0>		bd #	Size	Address	Way	Status
3,0>		3	1024			Normal
3,0>		3	1024			Normal
3,0>Board 3 Memory Configuration Test
3,0>    Memory Interleaving
3,0>	Total banks with 8MB SIMMs = 0
3,0>	Total banks with 32MB SIMMs = 0
3,0>	Total banks with 128MB SIMMs = 2
3,0>	Total banks with 256MB SIMMs = 0
3,0>	Overall memory default speed = 60ns
3,0>Do OPTIMAL INTLV
3,0>	Board 3 AC rev 5 RCTIME = 1 (Tras 71)
3,0>	Board 3 AC rev 5 RCTIME = 1 (Tras 71)
3,0>    Memory Refresh Enable
3,0>Board 3 SIMMs Test
3,0>    MP Memory SIMM Clear Test
3,0>	Memory Size is 2048Mbytes
3,0>	  CPU MID 7 clearing 00000000.00004000 to 00000000.40000000
3,0>	  CPU MID 6 clearing 00000000.40000000 to 00000000.80000000
3,0>	  CPU MID 6 clearing 00000000.00000000 to 00000000.00004000
3,0>    Memory Walking Rows and Columns Test
3,0>    MP Memory SIMM (6N RAM Patterns) Test
3,0>	Memory Size is 2048Mbytes
3,0>	  CPU MID 7 testing 00000000.00000000 to 00000000.40000000
3,0>	  CPU MID 6 testing 00000000.40000000 to 00000000.80000000
3,0>    MP Memory SIMM (moving inverse) Test
3,0>	Memory Size is 2048Mbytes
3,0>	  CPU MID 7 testing 00000000.00000000 to 00000000.40000000
3,0>	  CPU MID 6 testing 00000000.40000000 to 00000000.80000000
3,0>Slave CPU Functional Tests
3,0>	 Slave CPU MID 7 started
3,1>Board 3 Functional CPU 1 Test
3,1>    Dcache Init
3,1>    Dcache Enable Test
3,1>    Dcache Functionality Test
3,1>    Ecache Stress Test
3,1>    Ecache Functional Test
3,1>    CPU Dispatch (Multi-Scalar) Test
3,1>    SPARC Atomic Instructions Test
3,1>    SPARC Prefetch Instructions Test
3,1>    CPU Softint Registers and Interrupts Test
3,1>    Uni-Processor Cache Coherence Test
3,1>    Branch Memory Test
3,1>    SDB ECC CE Test
3,1>    SDB ECC Uncorrectable Test
3,1>    FPU Instruction Test
3,0>Board 3 Functional CPU 0 Test
3,0>    Dcache Init
3,0>    Dcache Enable Test
3,0>    Dcache Functionality Test
3,0>    Ecache Stress Test
3,0>    Ecache Functional Test
3,0>    CPU Dispatch (Multi-Scalar) Test
3,0>    SPARC Atomic Instructions Test
3,0>    SPARC Prefetch Instructions Test
3,0>    CPU Softint Registers and Interrupts Test
3,0>    Uni-Processor Cache Coherence Test
3,0>    Branch Memory Test
3,0>    SDB ECC CE Test
3,0>    SDB ECC Uncorrectable Test
3,0>    FPU Instruction Test
3,0>TESTING IO BOARD 1
3,0>Board 1 I/O FPROM Test
3,0>    I/O Board EPROM checksum Test
3,0>@(#) iPOST 3.4.29 2001/06/18 17:49
3,0> TESTING IO BOARD 1 ASICs
3,0> TESTING SysIO Port 0
3,0>Board 1 SysIO Registers Test
3,0>    SysIO Register Initialization
3,0>    IOMMU Registers and RAM Test
3,0>    Streaming Buffer Registers and RAM Test
3,0>    SBus Control and Config Registers Test
3,0>    SysIO RAM Initialization
3,0>Board 1 SysIO Functional Test
3,0>    Clear Interrupt Map and State Registers
3,0>    SysIO Interrupts  Test
3,0>    SysIO Timers/Counters Test
3,0>    IOMMU Virtual Address TLB Tag Compare Test
3,0>    Streaming Buffer Flush Test
3,0>    DMA Merge Buffer Test
3,0>    SYSIO ECC Correctable Test
3,0>    SYSIO ECC UnCorrectable Test
3,0>    SysIO Sbus Probe Test
3,0>    SysIO Register Initialization Test
3,0>    SysIO RAM Initialization Test
3,0>    Clear Interrupt Map and State Registers Test
3,0>Board 1 OnBoard IO Chipset (SOC) Test
3,0>    SOC SRAM Test
3,0>    SOC Registers Test
3,0>    SOC Interrupt Test
3,0>    Clear Interrupt Map and State Registers Test
3,0> TESTING SysIO Port 1
3,0>Board 1 SysIO Registers Test
3,0>    SysIO Register Initialization
3,0>    IOMMU Registers and RAM Test
3,0>    Streaming Buffer Registers and RAM Test
3,0>    SBus Control and Config Registers Test
3,0>    SysIO RAM Initialization
3,0>Board 1 SysIO Functional Test
3,0>    Clear Interrupt Map and State Registers
3,0>    SysIO Interrupts  Test
3,0>    SysIO Timers/Counters Test
3,0>    IOMMU Virtual Address TLB Tag Compare Test
3,0>    Streaming Buffer Flush Test
3,0>    DMA Merge Buffer Test
3,0>    SYSIO ECC Correctable Test
3,0>    SYSIO ECC UnCorrectable Test
3,0>    SysIO Sbus Probe Test
3,0>    SysIO Register Initialization Test
3,0>    SysIO RAM Initialization Test
3,0>    Clear Interrupt Map and State Registers Test
3,0>Board 1 OnBoard IO Chipset (FEPS) Test
3,0>    FAS366 Registers Test
3,0>    ESP FAS366 DVMA burst mode read/write Test
3,0>    FAS366 FIFO TO DMA Test
3,0>    DMA TO FAS366 FIFO Test
3,0>    FEPS (Ethernet) Registers Test
3,0>    FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test
3,0>    SysIO Register Initialization Test
3,0>    SysIO RAM Initialization Test
3,0>    Clear Interrupt Map and State Registers Test
3,0>IO BOARD 1 TESTED
3,0>SYSTEM LEVEL TESTING
3,0>Board 3 Cache Coherency Test
3,0>    Multi-Processor Cache Coherence Test
3,0>	Testing CPU MID 7
3,0>Probing for Disk System boards
3,0>Board 3 System Interrupts Test
3,0>    System Interrupts Test
3,0>ERROR: TEST=System Interrupts,SUBTEST=System Interrupts ID=1f.1
3,0>Component under test: Board 3 System Interrupt
3,0>Peripherial Power Supply PPSS_0 Failed
3,0>ERROR: TEST=System Interrupts,SUBTEST=System Interrupts ID=1f.1
3,0>Component under test: Board 3 System Interrupt
3,0>Peripherial Power Supply PPSS_0 Failed
3,0>Checking Power Supply Configuration
3,0>Power is more than adequate, load 2 ps 3
3,0>
3,0>	System Environmental Status
3,0>-----------------------------------------------------------------
3,0> Slot  Board Type    Temp   PS Stat      Perph PS
3,0>-----------------------------------------------------------------
3,0>  0  | Empty       |      |            | PP0 FAIL   |
3,0>  1  |+IO Type 4   | <42  | PS1 OK     | PP1 N_PRES |
3,0>  2  | Empty       |      |            |            |
3,0>  3  |+CPU/Memory  | <33  | PS3 OK     |            |
3,0>  4  | Empty       |      |            |            |
3,0>  5  | Empty       |      | PS5 OK     |            |
3,0>  6  | Empty       |      |            |            |
3,0>  7  | Empty       |      |            |            |
3,0> 16  | Clock Board | <36  |            |            |
3,0>-----------------------------------------------------------------
3,0>
3,0>	Precharge and Peripheral Power Supply Status
3,0>-----------------------------------------------------------------
3,0> V5_PCH   V3_PCH   V12_PCH  V5_PPCH  V5_AUX   V12_P    V5_P
3,0>-----------------------------------------------------------------
3,0> FAIL   | FAIL   | FAIL   | FAIL   | FAIL   | FAIL   | FAIL   |
3,0>-----------------------------------------------------------------
3,0>
3,0>	Miscellaneous Sensor Status
3,0>-----------------------------------------------------------------
3,0> RK_FAN   AC_FAN   KEY_FAN  CLK_33   CLK_50   NOT_BD_PRES
3,0>-----------------------------------------------------------------
3,0> FAIL   | OK     | OK     | OK     | OK     | ONE    |
3,0>-----------------------------------------------------------------
3,0>WARNING Test skipped, Interrupts Pending
3,0>    Check Board Present Test
3,0>    Board Present Interrupt Test
3,0>POST Failed
3,0>
3,0>	System Board Status
3,0>-----------------------------------------------------------------
3,0> Slot   Board Status     Board Type      Failures
3,0>-----------------------------------------------------------------
3,0>  0  | Not installed  |             |
3,0>  1  | Normal         |+IO Type 4   |
3,0>  2  | Not installed  |             |
3,0>  3  | Normal         |+CPU/Memory  |
3,0>  4  | Not installed  |             |
3,0>  5  | Not installed  |             |
3,0>  6  | Not installed  |             |
3,0>  7  | Not installed  |             |
3,0> 16  | Online/failure | Clock Board | PPS_DC_FAIL AC_FAIL DISK_FAN_FAIL
3,0>-----------------------------------------------------------------
3,0>
3,0>	CPU Module Status
3,0>-----------------------------------------------------------------
3,0> MID  OK  Cache  Speed   Version
3,0>-----------------------------------------------------------------
3,0>  6 | y | 8192  |  400  | 00170011.a0000507
3,0>  7 | y | 8192  |  400  | 00170011.a0000507
3,0>-----------------------------------------------------------------
3,0>System Frequency (MHz),fcpu=400, fmod=200, fsys=100, fgen=400
3,0>	Populated Memory Bank Status
3,0>		bd #	Size	Address	Way	Status
3,0>		3	1024	0	2	Normal
3,0>		3	1024	1	2	Normal
3,0>
3,0>
	POST COMPLETE
3,0>Entering OBP

ttya initialized
Using POST's System Configuration
Setting up memory
Starting CPU ID 7 
Clock board TOD does not match TOD on any IO board.
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II 
Probing UPA Slot at 2,0   sbus fhc ac environment flashprom eeprom sbus-speed co
unter-timer 
Probing UPA Slot at 3,0   sbus counter-timer 
Probing /sbus@2,0 at d,0  SUNW,socal sf ssd sf ssd 
Probing /sbus@2,0 at 1,0  Nothing there
Probing /sbus@2,0 at 2,0  sd Probing Fibre Channel Adapter
fcaw Testing Fibre Channel Adapter
BCSR Test Passed
PEROM Checksum OK, = 18c932 
Interrupt Level = 3 
Interrupts Level = 3 
SCSI Initiator ID = 7d 
Current WWN = 10 0 0 e0 69 41 16 72 
Default WWN = 10 0 0 e0 69 41 16 72 
Serial Number = 5746 
Boot Node 0 WWN = ff ff ff ff ff ff ff ff 
Boot Node 1 WWN = ff ff ff ff ff ff ff ff 
Testing only Tachyon registers
F_LSTAT1  error
SelfTest Failed

Probing /sbus@3,0 at 3,0  SUNW,hme SUNW,fas sd st 
Probing /sbus@3,0 at 0,0  QLGC,isp invalid command
sd st 
screen not found.
Can't open input device.
Keyboard not present.  Using ttya for input and output.
Using POST's System Configuration
Setting up memory
Starting CPU ID 7 
Clock board TOD does not match TOD on any IO board.
fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC
-II 
Probing UPA Slot at 2,0   sbus fhc ac environment flashprom eeprom sbus-speed co
unter-timer 
Probing UPA Slot at 3,0   sbus counter-timer 
Probing /sbus@2,0 at d,0  SUNW,socal sf ssd sf ssd 
Probing /sbus@2,0 at 1,0  Nothing there
Probing /sbus@2,0 at 2,0  sd Probing Fibre Channel Adapter
fcaw Testing Fibre Channel Adapter
BCSR Test Passed
PEROM Checksum OK, = 18c932 
Interrupt Level = 3 
Interrupts Level = 3 
SCSI Initiator ID = 7d 
Current WWN = 10 0 0 e0 69 41 16 72 
Default WWN = 10 0 0 e0 69 41 16 72 
Serial Number = 5746 
Boot Node 0 WWN = ff ff ff ff ff ff ff ff 
Boot Node 1 WWN = ff ff ff ff ff ff ff ff 
Testing only Tachyon registers
F_LSTAT1  error
SelfTest Failed

Probing /sbus@3,0 at 3,0  SUNW,hme SUNW,fas sd st 
Probing /sbus@3,0 at 0,0  QLGC,isp invalid command
sd st 

4-slot Sun Enterprise 3000, No Keyboard
OpenBoot 3.2.30, 2048 MB memory installed, Serial #9102161.
Copyright 2002 Sun Microsystems, Inc.  All rights reserved
Ethernet address 8:0:20:8a:e3:51, Host ID: 808ae351.



unexpected sxp interrupt 
invalid command
Boot device: net  File and args: 
Using Onboard Transceiver - Timeout waiting for AutoNegotiation Status to be upd
ated. 
Timeout reading Link status. Check cable and try again. 
Timeout waiting for AutoNegotiation Status to be updated. 
Timeout reading Link status. Check cable and try again. 
Timeout waiting for AutoNegotiation Status to be updated. 
Timeout reading Link status. Check cable and try again. 
AutoNegotiation Timeout. 
Check Cable or Contact your System Administrator. 
Link Down.
Setting up Network Link and Speed. 

{6} ok probe-scsi
{6} ok